1. Field of the Invention
The present invention relates to a semiconductor memory having static memory cells. In particular, the present invention relates to a semiconductor memory having bit lines of hierarchical structure.
2. Description of the Related Art
Semiconductor memories are growing in memory capacity as the transistor structure gets finer. Meanwhile, with finer transistor structures, logic LSIs such as a microcomputer are improving in operating frequency. For the sake of improved operating frequencies, shorter access time is thus required of the semiconductor memories. DRAMs and such semiconductor memories have bit lines of hierarchical structure in view of reduced access time. To meet the need for a further speedup, hierarchization has been recently contemplated of the wiring structure of bit lines even in semiconductor memories having static memory cells (hereinafter, referred to as SRAMs).
Japanese Unexamined Patent Application Publication No. Hei 9-246482 discloses a circuit technology and a layout technology for a hierarchical bit line structure of a DRAM.
Japanese Unexamined Patent Application Publication No. Hei 5-128859 discloses a hierarchical bit line structure of a DRAM in which bit lines for read and bit lines for write are formed independently of each other. The global bit lines for read are connected to the drains of transistors. The gates of these transistors are connected to local bit lines. The global bit lines are precharged to a circuit internal step-down voltage which is a power supply voltage VCC stepped down by a load circuit. The system that local bit lines in connection with memory cells are connected to the gates of transistors is typically referred to as direct sense system.
Japanese Unexamined Patent Application Publication No. 2001-67876 discloses a hierarchical bit line structure of a DRAM in which local bit lines and global bit lines are connected to each other through CMOS transmission gates. The global bit lines are precharged to an internal step-down voltage VDL.
By the way, DRAMs store data by retaining charges corresponding to the data into their memory cells. When the memory cells are accessed, the storage charges of the memory cells are shared between bit lines. Sense amplifiers amplify the small voltage variations on the bit lines. Since the slight voltage variations on the bit lines are detected by the sense amplifiers, the DRAMs are susceptible to noise in accessing the memory cells. The influence of power supply noise and the like on the bit lines is thus reduced by, for example, using an internal step-down voltage lower than the power supply voltage as the precharging voltage of the global bit lines.
SRAM memory cells are made of flip-flops. The flip-flops store data written to the memory cells (logic “1” or logic “0”) in the form of, for example, a power supply voltage or a ground voltage. When the memory cells are accessed, the flip-flops output the stored power supply voltage or ground voltage to bit lines directly. Consequently, SRAMs are less susceptible to power supply noise than DRAMs are, and will not malfunction even if the power supply voltage is used as the precharging voltage.
In the hierarchical bit line structure (direct sense system) disclosed in Japanese Unexamined Patent Application Publication No. Hei 5-128859, the global bit lines undergo currents that flow in one direction alone, or from the load circuit (precharging circuit) to the memory cells. Electromigration criteria on the wiring through which currents flow in one direction are stricter that those on wiring through which currents flow in both directions. In other words, the wiring through which currents flow in one direction is more prone to disconnection resulting from electromigration than the wiring through which currents flow in both directions is.
In DRAMS, however, the global bit lines are supplied with the internal step-down voltage. Hence, at ordinary wiring widths, electromigration does not matter. On the other hand, in SRAMs in which the global bit lines are precharged to the power supply voltage, the currents flowing through the global bit lines are higher than in DRAMs. Consequently, when an SRAM adopts a hierarchical bit line structure of direct sense system, i.e., when an SRAM is provided with global bit lines through which currents flow in one direction, the global bit lines must be given a wiring width greater than heretofore so as to avoid disconnection resulting from electromigration.
In general, SRAMs have date terminals of 8 bits or broader bit widths such as 16, 32, 64, 72, 144, and 288 bits. The number of global bit lines in a chip increases depending on the number of bits of the data terminals. Consequently, there is the problem that broadening the global bit lines in wiring width can cause an increase in chip size as well as in chip cost.